module main;

  reg clk, reset;
  reg  [31:0] x; 
  reg  [31:0] z;
  wire [15:0] y1,y2;
  wire        rdy1,rdy2;

  sqrt32 dut1 (clk, rdy1, reset, x, y1);

  sqrt32 dut2 (clk, rdy2, reset, z, y2);

  always #10 clk = ~clk;

  initial begin
     clk = 0;
     reset = 1;

     if (! $value$plusargs("x=%d", x)) begin
        $display("ERROR: please specify +x=<value> to start.");
        $finish;
     end

     if (! $value$plusargs("z=%d", z)) begin
        $display("ERROR: please specify +z=<value> to start.");
        $finish;
     end


     #35 reset = 0;

     wait (rdy1) $display("y1=%d", y1);
     wait (rdy2) $display("y2=%d", y2);
     $finish;
  end // initial begin

endmodule // main